VHDL assignment slice not implemented? -

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is possible specify bit range assigned on left side of assignment?

eg. r(15 downto 8) <= r(15 downto 8) -d;

the above gives me compiler error: error 722: assignment signal slice not implemented. i've tried googling error no avail.

however works:

r <= r(15 downto 8) - d;

assignments slices allowed. tool using? size of d? pay attention result sizes. if size of d larger r, result size matches size of d.

what happens in following assignments:

r(15 downto 0) <= r(15 downto 8) - d ;

if assignment works, need slice d:

r(15 downto 8) <= r(15 downto 8) - d(7 downto 0);

if not it, rest of code like?


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